Computer Organization Interview Questions and Answers

YASH PAL,

Here in this article, we are going to see basic to advanced Computer Organization Interview Questions and Answers for Interview preparation, University Exams.

Spatial locality refers to the problem that once a location is referenced

  1. it will not be referenced again
  2. it will be referenced again
  3. a nearby location will be referenced soon
  4. none of the above

Answer – (3) a nearby location will be referenced soon

A polled interrupt is handled by

  1. software
  2. hardware
  3. firmware
  4. none of these

Answer – (1) software

Consider the following register-transfer language

R3 <– R3 + M[R1 + R2]

where R1, R2 are the CPU registers and M is a memory location in primary memory. which addressing mode is suitable for the above register-transfer language?

  1. immediate
  2. indexed
  3. direct
  4. displacement

Answer – (2) indexed

Which memory unit has the lowest access time?

  1. cache
  2. registers
  3. magnetic disk
  4. main memory

Answer – (2) registers

The computer performs all mathematical and logical operations inside its

  1. memory unit
  2. central processing unit
  3. output unit
  4. visual display unit

Answer – (2) central processing unit

Which of the following are examples of input devices?

  1. visual display unit, dot matrix printer, laser printer
  2. keyboard, mouse, optical mark reader
  3. arithmetic and logic unit, the control unit
  4. RAM, ROM, PROM

Answer – (2) Keyboard, mouse, optical mark reader

In a 16-bit instruction code format 3-bit operation code, 12-bit address, and 1-bit are assigned for address mode designation. For indirect addressing, the mode bit is

  1. 0
  2. 1
  3. pointer
  4. off-set

Answer – (2) 1

What do CISC and RISC mean?

  1. common instruction set controller and rare instruction set controller
  2. complex instruction set controller and reduced instruction set controller
  3. compiled instruction set source code and recompiled instruction source code
  4. none of the above

Answer – (4) None of the above

During the DMA transfer. DMA controller takes over the buses to manage the transfer

  1. directly from the CPU to the memory
  2. directly from memory to the CPU
  3. indirectly between the I/O device and memory
  4. directly between the I/O device and memory

Answer – (4) directly between the I/O device and memory

Booth’s algorithm is used in floating-point

  1. addition
  2. subtraction
  3. multiplication
  4. division

Answer – (3) multiplication

Match List-I with List-II and select the correct answer using the codes given below the lists:

List-ILis-II
A. Regs[R4] ← Regs[R4] + Regs[R3]1. immediate
B. Regs[R4] ← Regs[R4] + 32. register
C. Regs[R4] ← Regs[R4] + Mem[Regs[R1]]3. displacement

  A   B   C

  1.  3   2   1
  2.  2   1   3
  3.  1   2   3
  4.  3   1   2

Answer – (2) 2 1 3

A 32-bit address bus allows access to a memory of capacity

  1. 64 MB
  2. 16 MB
  3. 1 GB
  4. 4 GB

Answer – (4) 4 GB

Pipelining improves CPU performance due to

  1. reduced memory access time
  2. increased clock speed
  3. the introduction of parallelism
  4. additional functional units

Answer – (3) the introduction of parallelism

The system bus is made up of

  1. data bus
  2. data bus and address bus
  3. data bus and control bus
  4. the data bus, control bus, and address bus

Answer – (4) the data bus, control bus, and address bus

Cache memory enhances

  1. memory capacity
  2. memory access time
  3. effective memory access time
  4. secondary storage access time

Answer – (3) effective memory access time

Cache memory

  1. has greater capacity than RAM
  2. is faster to access than CPU registers
  3. is permanent storage
  4. faster to access than RAM

Answer – (4) faster to access than RAM

An instruction cycle refers to

  1. fetching an instruction
  2. clock speed
  3. fetching, decoding, and executing an instruction
  4. executing an instruction

Answer – (3) fetching, decoding, and executing an instruction

Given a 5-stage pipeline with stages taking 1, 2, 3, 1, and 1 unit of time, the clock period of the pipeline is

  1. 8
  2. 1/8
  3. 1/3
  4. 3

Answer – (4) 3

A hardware interrupt is

  1. also called an internal interrupt
  2. also called an external interrupt
  3. an I/O interrupt
  4. a clock interrupt

Answer – (2) also called an external interrupt

The read/write line

  1. belongs to the data bus
  2. belongs to the control bus
  3. belongs to the address bus
  4. CPU bus

Answer – (2) belongs to the control bus

Note – more questions and answers will be added from time to time.

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